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functional block diagram (dip package) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ad1865 +v s nc trim msb sj dl ll dgnd agnd v out i out r f ? s i out +v l v out trim msb lr clk dr agnd sj r f 18-bit latch 18-bit d/a reference 18-bit latch 18-bit d/a reference nc = no connect rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a complete dual 18-bit 16 3 f s audio dac ad1865 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features dual serial input, voltage output dacs no external components required 110 db snr 0.003% thd+n operates at 16 3 oversampling per channel 6 5 volt operation cophased outputs 116 db channel separation pin compatible with ad1864 dip or soic packaging applications multichannel audio applications compact disc players multivoice keyboard instruments dat players and recorders digital mixing consoles multimedia workstations product description the ad1865 is a complete, dual 18-bit dac offering excellent thd+n and snr while requiring no external components. two complete signal channels are included. this results in cophased voltage or current output signals and eliminates the need for output demultiplexing circuitry. the monolithic ad1865 chip includes cmos logic elements, bipolar and mos linear ele- ments and laser-trimmed thin-film resistor elements, all fabri- cated on analog devices abcmos process. the dacs on the ad1865 chip employ a partially segmented architecture. the first four msbs of each dac are segmented into 15 elements. the 14 lsbs are produced using standard r-2r techniques. segment and r-2r resistors are laser trimmed to pro- vide ex tremely low total harmonic distortion. this architecture minimizes errors at major code transitions resulting in low out- put glitch and eliminating the need for an external deglitcher. when used in the current output mode, the ad1865 provides two 1 ma output signals. each channel is equipped with a high performance output am- plifier. these amplifiers achieve fast settling and high slew rate, producing 3 v signals at load currents up to 8 ma. each out- put amplifier is short-circuit protected and can withstand indefi- nite short circuits to ground. the ad1865 was designed to balance two sets of opposing re- quirements, channel separation and dac matching. high chan- nel separation is the result of careful layout. at the same time, both channels of the ad1865 have been designed to ensure matched gain and linearity as well as tracking over time and temperature. this assures optimum performance when used in stereo and multi-dac per channel applications. a versatile digital interface allows the ad1865 to be directly connected to standard digital filter chips. this interface employs five signals: data left (dl), data right (dr), latch left (ll), latch right (lr) and clock (clk). dl and dr are the serial input pins for the left and right dac input registers. input data bits are clocked into the input register on the rising edge of clk. a low-going latch edge updates the respective dac out- put. for systems using only a single latch signal, ll and lr may be connected together. for systems using only one data signal, dr and dl may be connected together. the ad1865 operates with 5 v power supplies. the digital supply, v l , can be separated from the analog supplies, v s and Cv s , for reduced digital feedthrough. separate analog and digital ground pins are also provided. the ad1865 typically dissipates only 225 mw, with a maximum power dissipation of 260 mw. the ad1865 is packaged in both a 24-pin plastic dip and a 28-pin soic package. operation is guaranteed over the temper- ature range of C25 c to +70 c and over the voltage supply range of 4.75 v to 5.25 v. product highlights 1 1. the ad1865 is a complete dual 18-bit audio dac. 1 2. 110 db signal-to-noise ratio for low noise operation. 1 3. thd+n is typically 0.003%. 1 4. interchannel gain and midscale matching. 1 5. output voltages and currents are cophased. 1 6. low glitch for improved sound quality. 1 7. both channels are 100% tested at 16 f s . 1 8. low poweronly 225 mw typ, 260 mw max. 1 9. five-wire interface for individual dac control. 10. 24-pin dip or 28-pin soic packages available. obsolete
rev. 0 C2C ad1865Cspecifications (t a = +25 8 c, +v l = +v s = +5 v and Cv s = C5 v, f s = 705.6 khz, no msb adjustment or deglitcher) parameter min typ max unit resolution 18 bits digital inputs v ih 2.0 +v l v v il 0.8 v i ih , v ih = +v l 1.0 m a i il , v il = 0.4 v C10 m a clock input frequency 13.5 mhz accuracy gain error 0.2 1.0 % of fsr interchannel gain matching 0.3 0.8 % of fsr midscale error 4 mv interchannel midscale matching 5 mv gain linearity (0 db to C90 db) <2 db drift (0 c to +70 c) gain drift 25 ppm of fsr/ c midscale drift 4 ppm of fsr/ c total harmonic distortion + noise* 0 db, 990.5 hz ad1865n, r 0.004 0.006 % ad1865n-j, r-j 0.003 0.004 % 20 db, 990.5 hz ad1865n, r 0.010 0.040 % ad1865n-j, r-j 0.010 0.020 % C60 db, 990.5 hz ad1865n, r 1.0 4.0 % ad1865n-j, r-j 1.0 2.0 % channel separation* 0 db, 990.5 hz 110 116 db signal-to-noise ratio* (20 hz to 30 khz) 107 110 db d-range* (with a-weight filter) C60 db, 990.5 hz ad1865n, r 88 100 db ad1865n-j, r-j 94 100 db output voltage output configuration output range ( 1%) 6 2.94 3.0 6 3.06 v output impedance 0.1 w load current 8ma short circuit duration indefinite to common current output configuration bipolar output range ( 30%) 1ma output impedance ( 30%) 1.7 k w power supply +v l and +v s 4.75 5.0 5.25 v Cv s C5.25 C5.0 C4.75 v +i, +v l and +v s = +5 v 22 26 ma Ci, Cv s = C5 v C23 C26 ma power dissipation, +v l = +v s = +5 v, Cv s = C5 v 225 260 mw temperature range specification 0 +25 +70 c operation C25 +70 c storage C60 +100 c warmup time 1 min specifications shown in boldface are tested on production units at final test without optional msb adjustment. *tested in accordance with eiaj test standard cp-307 with 18-bit data. specifications subject to change without notice. obsolete
ad1865 rev. 0 C3C absolute maximum ratings* v l to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 6.0 v v s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 6.0 v Cv s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . C6.0 v to 0 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v digital inputs to dgnd . . . . . . . . . . . . . . . . . . . . . C0.3 to v l short circuit protection . . . . . . . . indefinite short to ground soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1865 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package model range thd+n @ fs option* ad1865n C25 c to +70 c 0.006% n-24a ad1865n-j C25 c to +70 c 0.004% n-24a ad1865r C25 c to +70 c 0.006% r-28 ad1865r-j C25 c to +70 c 0.004% r-28 *n = plastic dip, r = small outline ic package. pin designations dip soic 1 122 Cv s negative analog supply 1 2 23 trim right channel trim network connection 1 3 24 msb right channel trim potentiometer wiper connection 1 426 i out right channel output current 1 5 28 agnd analog common pin 1 6 1 1 sj right channel amplifier summing junc tion 1 7 1 2r f right channel feedback resistor 1 8 1 3v out right channel output voltage 1 9 1 4+v l positive digital supply 10 1 5 dr right channel data input pin 11 1 6 lr right channel latch pin 12 1 7 clk clock input pin 13 1 8 dgnd digital common pin 14 1 9 ll left channel latch pin 15 10 dl left channel data input pin 16 11, 16, 18 nc no internal connection* 25, 27 17 12 v out left channel output voltage 18 13 r f left channel feedback resistor 19 14 sj left channel amplifier summing junction 20 15 agnd analog common pin 21 17 i out left channel output current 22 19 msb left channel trim potentiometer wiper connection 23 20 trim left channel trim network connection 24 21 +v s positive analog supply *pin 16 has no internal connection; Cv l from ad1864 dip socket can be safely applied. pinout (24-pin dip package) 14 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 13 top view (not to scale) ad1865 +v s nc trim msb sj dl ll dgnd agnd v out i out r f ? s i out +v l v out trim msb lr clk dr agnd sj r f left channel right channel nc = no connect (28-pin soic package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 top view (not to scale) ad1865 sj r f v out +v l dr lr clk dl ll dgnd nc v out r f sj agnd nc i out nc msb trim ? s +v s trim msb nc i out nc agnd nc = no connect obsolete
ad1865 rev. 0 C4C total harmonic distortion + noise total harmonic distortion plus noise (thd+n) is defined as the ratio of the square root of the sum of the squares of the am- plitudes of the harmonics and noise to the value of the funda- mental input frequency. it is usually expressed in percent. thd+n is a measure of the magnitude and distribution of lin- earity error, differential linearity error, quantization error and noise. the distribution of these errors may be different, depend- ing on the amplitude of the output signal. therefore, to be most useful, thd+n should be specified for both large (0 db) and small (C20 db, C60 db) signal amplitudes. thd+n measure- ments for the ad1865 are made using the first 19 harmonics and noise out to 30 khz. signal-to-noise ratio the signal-to-noise ratio is defined as the ratio of the amplitude of the output when a full-scale code is entered to the amplitude of the output when a midscale code is entered. it is measured using a standard a-weight filter. snr for the ad1865 is mea- sured for noise components out to 30 khz. channel separation channel separation is defined as the ratio of the amplitude of a full-scale signal appearing on one channel to the amplitude of that same signal which couples onto the adjacent channel. it is usually expressed in db. for the ad1865 channel separation is measured in accordance with eiaj standard cp-307, section 5.5. d-range distortion d-range distortion is equal to the value of the total harmonic distortion + noise (thd+n) plus 60 db when a signal level of C60 db below full scale is reproduced. d-range is tested with a 1 khz input sine wave. this is measured with a standard a-weight filter as specified by eiaj standard cp-307. gain error the gain error specification indicates how closely the output of a given channel matches the ideal output for given input data. it is expressed in % of fsr and is measured with a full-scale out- put signal. interchannel gain matching the gain matching specification indicates how closely the ampli- tudes of the output signals match when producing identical in- put data. it is expressed in % of fsr (full-scale range = 6 v for the ad1865) and is measured with full-scale output signals. midscale error midscale error is the deviation of the actual analog output of a given channel from the ideal output (0 v) when the twos complement input code representing half scale is loaded into the input register of the dac. it is expressed in mv and is mea- sured with half-scale output signals. interchannel midscale matching the midscale matching specification indicates how closely the amplitudes of the output signals of the two channels match when the twos complement input code representing half scale is loaded into the input register of both channels. it is expressed in mv and is measured with half-scale output signals. functional description the ad1865 is a complete, monolithic, dual 18-bit audio dac. no external components are required for operation. as shown in the block diagram, each chip contains two voltage references, two output amplifiers, two 18-bit serial input registers and two 18-bit dacs. the voltage reference section provides a reference voltage for each dac circuit. these voltages are produced by low-noise bandgap circuits. buffer amplifiers are also included. this com- bination of elements produces reference voltages that are unaf- fected by changes in temperature and age. the output amplifiers use both mos and bipolar devices and incorporate an all npn output stage. this design technique produces higher slew rate and lower distortion than previous techniques. frequency response is also improved. when com- bined with the appropriate on-chip feedback resistor, the output op amps convert the output current to output voltages. the 18-bit d/a converters use a combination of segmented de- coder and r-2r architecture to achieve consistent linearity and differential linearity. the resistors which form the ladder struc- ture are fabricated with silicon chromium thin film. laser trim- ming of these resistors further reduces linearity errors resulting in low output distortion. the input registers are fabricated with cmos logic gates. these gates allow the achievement of fast switching speeds and low power consumption, contributing to the low glitch and low power dissipation of the ad1865. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ad1865 +v s nc trim msb sj dl ll dgnd agnd v out i out r f ? s i out +v l v out trim msb lr clk dr agnd sj r f 18-bit latch 18-bit d/a reference 18-bit latch 18-bit d/a reference nc = no connect ad1865 block diagram (dip package) obsolete
rev. 0 C5C 100 90 70 048 frequency ?khz thd+n ?db 80 12 16 0db 80 100 120 110 90 0 frequency ?khz channel separation ?db 4 12 16 8 figure 1. thd+n (db) vs. frequency (khz) figure 2. channel separation (db) vs. frequency (khz) thd+n ?% 10 1 .1 .01 .001 ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 temperature ? c ?0db ?0db 0db figure 3. thd+n (%) vs. temperature ( c) 100 90 80 70 60 50 40 500 1000 1500 2000 2500 3000 load resistance ? w thd+n ?db 0 figure 4. thd+n (db) vs. load resistance ( w ) thd+n ?db 10 8 6 4 2 0 ? ? ? ? ?0 ?00 60 40 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 input amplitude ?db figure 5. gain linearity (db) vs. input amplitude (db) typical performance dataCad1865 obsolete
grounding recommendations the ad1865 has three ground pins, two labeled agnd and one labeled dgnd. agnd, the analog ground pins, are the high quality ground references for the device. to minimize distortion and reduce crosstalk between channels, the analog ground pins should be connected together only at the analog common point in the system. as shown in figure 6, the agnd pins should not be connected at the chip. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 ad1865 nc = no connect ? s trim msb i out agnd sj r f v out +v l dr lr clk +v s trim msb i out agnd sj r f v out nc dl ll dgnd ?nalog supply digital supply v out analog supply v out digital common figure 6. recommended circuit schematic the digital ground pin returns ground current from the digital logic portions of the ad1865 circuitry. this pin should be con- nected to the digital common pin in the system. other digital logic chips should also be referred to that point. the analog and digital grounds should be connected together at one point in the system, preferably at the power supply. power supplies and decoupling the ad1865 has three power supply input pins. v s provides the supply voltages which operate the analog portions of the dac including the voltage references, output amplifiers and control amplifiers. the v s supplies are designed to operate from 5 v supplies. each supply should be decoupled to analog common using a 0.1 m f capacitor in parallel with a 10 m f capacitor. good engineering practice suggests that the bypass capacitors be placed as close as possible to the pack age pins. this minimizes the parasitic inductive effects of printed circuit board traces. the +v l supply operates the digital portions of the chip includ- ing the input shift registers and the input latching circuitry. this supply should be bypassed to digital common using a 0.1 m f capacitor in parallel with a 10 m f capacitor. +v l oper- ates with a +5 v supply. in order to assure proper operation of the ad1865, Cv s must be the most negative power supply volt- age at all times. though separate positive power supply pins are provided for the analog and digital portions of the ad1865, it is also possible to use the ad1865 in systems featuring a single +5 v power supply. in this case, both the +v s and +v l input pins should be connected to the single +5 v power supply. this feature allows reduction of the cost and complexity of the system power supply. ad1865Canalog circuit consideration rev. 0 C6C as with most linear circuits, changes in the power supplies will affect the output of the dac. analog devices recommends that well regulated power supplies with less than 1% ripple be incor- porated into the design of an audio system. distortion performance and testing the thd+n figure of an audio dac represents the amount of undesirable signal produced during reconstruction and playback of an audio waveform. the thd+n specification, therefore, provides a direct method to classify and choose an audio dac for a desired level of performance. figure 1 illustrates the typ- ical thd+n performance of the ad1865 versus frequency. a load impedance of at least 1.5 k w is recommended for best thd+n performance. analog devices tests and grades all ad1865s on the basis of thd+n performance. during the distortion test, a high-speed digital pattern generator transmits digital data to each channel of the device under test. eighteen-bit data is transmitted at 705.6 khz (16 f s ). the test waveform is a 990.5 hz sine wave with 0 db, C20 db and C60 db amplitudes. a 4096 point fft calculates total harmonic distortion + noise, signal-to-noise ratio, d-range and channel separation. no deglitchers or msb trims are used in the testing of the ad1865. optional msb adjustment use of optional adjust circuitry allows residual distortion error to be eliminated. this distortion is especially important when low amplitude signals are being reproduced. the msb adjust circuitry is shown in figure 7. the trim potentiometer should be adjusted to produce the lowest distortion using an input sig- nal with a C60 db amplitude. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 ad1865 nc = no connect ? s trim msb i out agnd sj r f v out +v l dr lr clk +v s trim msb i out agnd sj r f v out nc dl ll dgnd 200kw 100kw 470kw 470kw 100kw 200kw figure 7. optional thd+n adjust circuitry obsolete
rev. 0 C7C current output mode one or both channels of the ad1865 can be operated in current output mode. i out can be used to directly drive an external current-to-voltage (i-v) converter. the internal feedback resis- tor, r f , can still be used in the feedback path of the external i-v converter, thus assuring that r f tracks the dac over time and temperature. of course, the ad1865 can also be used in voltage output mode in order to utilize the onboard i-v converter. voltage output modes as shown on the block diagram, each channel of the ad1865 is complete with an i-v converter and a feedback resistor. these can be connected externally to provide direct voltage output from one or both ad1865 channels. figure 6 shows these con- nections. i out is connected to the summing junction, sj. v out is connected to the feedback resistor, r f . this implementation results in the lowest possible component count and achieves the specifications shown on the specifications page while operating at 16 f s . l s b l s b m s b m s b clk dl dr ll lr figure 8. ad1865 control signals input data data is transmitted to the ad1865 in a bit stream composed of 18-bit words with a serial, twos complement, msb first format. data left (dl) and data right (dr) are the serial inputs for the left and right dacs, respectively. similarly, latch left (ll) and latch right (lr) update the left and right dacs. the fall- ing edge of ll and lr cause the last 18 bits which were clocked into the serial registers to be shifted into the dacs, thereby updating the dac outputs. left and right channels share the clock (clk) signal. data is clocked into the input registers on the rising edge of clk. figure 8 illustrates the general signal requirements for data transfer for the ad1865. timing figure 9 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished prop- erly. the input pins of the ad1865 are both ttl and 5 v cmos compatible. the minimum clock rate of the ad1865 is at least 13.5 mhz. this clock rate allows data transfer rates of 2 , 4 , 8 and 16 f s (where f s equals 44.1 khz). clk dl/dr ll/lr >74.1ns >30ns >30ns >40ns >15ns >40ns >40ns >30ns >15ns >15ns msb 1st bit 2nd bit lsb 18th bit next word bits clocked to shift register internal dac input register updated with 18 most recent bits figure 9. ad1865 timing diagram digital circuit considerationsCad1865 obsolete
ad1865 rev. 0 C8C 18-bit cd player design figure 10 illustrates an 18-bit cd player design incorporating an ad1865 d/a converter, an ne5532 dual op amp and the sm5813 digital filter chip manufactured by npc. in this de- sign, the sm5813 filter transmits left and right digital data to both channels of the ad1865. the left and right latch signals, ll and lr, are both provided by the word clock signal (wcko) of the digital filter. the digital filter supplies data at an 8 f s oversample rate to each channel. the digital data is converted to analog output voltages by the output amplifiers on the ad1865. note that no external compo- nents are required by the ad1865. also, no deglitching cir- cuitry is required. an ne5532 dual op amp is used to provide the output antialias filters required for adequate image rejection. one 2-pole filter section is provided for each channel. an additional pole is cre- ated from the combination of the internal feedback resistors (r f ) and the external capacitors c1 and c2. for example, the nominal 3 k w r f with a 360 pf capacitor for c1 and c2 will place a pole at approximately 147 khz, effectively eliminating all high frequency noise components. low distortion, superior channel separation, low power con- sumption and a low parts count are all realized by this simple design. 2 4 5 6 1 3 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ad1865 +v s trim msb sj dl ll dgnd agnd v out r f ? s i out +v l v out trim msb lr clk dr agnd sj r f 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 c1 c2 1 2 3 4 5 6 7 8 ? s +v s left channel output right channel output ?v analog supply +5v analog supply +5v digital supply bcko wcko dol dor v dd dg ow20 sm5813ap/ apt nc ne5532 i out vs s1 vs s2 ow18 figure 10. complete 8 f s 18-bit cd player obsolete
ad1865 rev. 0 C9C multichannel digital keyboard design figure 11 illustrates how to cascade ad1865s to add multiple voices to an electronic musical instrument. in this example, the data and clock signals are shared between all six dacs. as the data representing an output for a specific voice is loaded, the ap- propriate dac is updated. for example, after the 18-bits repre- senting the next output value for voice 4 is clocked out on the data line, then voice 4 load is pulled low. this produces a new output for voice 4. furthermore, all voices can be returned to the same output by pulling all six load signals low. in this application, the advantages of choosing the ad1865 are clear. its flexible digital interface allows the clock and data to be shared among all dacs. this reduces pc board area require- ments and also simplifies the actual layout of the board. the low power requirements of the ad1865 (approximately 225 mw) is an advantage in a multiple dac system where any power advan- tage is multiplied by the number of dacs used. the ad1865 requires no external components, simplifying the design, reduc- ing the total number of components required and enhancing reliability. ad1865 trim msb sj agnd v out i out r f ? s +v l lr clk dr 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 +5v analog supply ?v analog supply voice 1 output ad1865 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ad1865 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 voice 1 load analog common voice 3 load data voice 2 load clock voice 2 output voice 3 output voice 4 output voice 5 output voice 6 output voice 6 load voice 5 load voice 4 load digital common +5v digital supply +v s dl ll dgnd i out v out trim msb agnd sj r f nc trim msb sj agnd v out i out r f ? s +v l lr clk dr trim msb sj agnd v out i out r f ? s +v l lr clk dr +v s dl ll dgnd i out v out trim msb agnd sj r f nc +v s dl ll dgnd i out v out trim msb agnd sj r f nc figure 11. cascaded ad1865s in a multichannel keyboard instrument obsolete
ad1865 rev. 0 C10C additional applications figures 12 through 14 show connection diagrams for the ad 1865 and standard digital filter chips from yamaha, npc and sony. each figure is an example of cophase operation operating at 8 f s for each channel. the 2-pole rauch low-pass filters shown in figure 10 can be used with all of the applications shown in this data sheet. 24 23 22 19 21 20 18 17 16 15 14 13 12 2 1 3 4 5 6 7 9 11 10 8 ad1865 msb i out dl ll dgnd v out i out trim msb agnd sj trim sj agnd v out r f ? s +v l lr clk dr +v s r f +5v digital supply lpf lpf right channel output left channel output ?v analog supply +5v analog supply 1 2 3 4 5 6 7 8 12 11 10 9 13 16 15 14 v ss shl v dd2 shr st bco wco dlo v dd1 dro ym3434 nc 16/18 figure 12. ad1865 with yamaha ym3434 digital filter 24 23 22 19 21 20 18 17 16 15 14 13 12 2 1 3 4 5 6 7 9 11 10 8 ad1865 msb i out dl ll dgnd v out i out trim msb agnd sj trim sj agnd v out r f ? s +v l lr clk dr +v s r f +5v digital supply lpf right channel output left channel output ?v analog supply +5v analog supply nc lpf 1 2 3 4 5 6 7 8 12 11 10 9 13 16 15 14 v ss dol dor wdco bcko v dd sm5818 omod1 omod2 figure 14. ad1865 with npc sm5818ap digital filter 24 23 22 19 21 20 18 17 16 15 14 13 12 2 1 3 4 5 6 7 9 11 10 8 ad1865 msb i out dl ll dgnd v out i out trim msb agnd sj trim sj agnd v out r f ? s +v l lr clk dr +v s r f lpf right channel output left channel output ?v analog supply +5v analog supply 16.9344 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 19 18 17 16 14 20 15 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 gnd test test test test test xin v dd v dd lfs sony/12s test test test dpol out 16/18 le/ ws datar gnd gnd datal bcko cxd1244s nc lpf +5v digital supply figure 13. ad1865 with sony cxd1244s digital filter obsolete
ad1865 rev. 0 C11C other digital audio components available from analog devices 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ad1856 ? s dgnd nc clk le data ? l +v l nc no connect = +v s trim msb adj i out agnd sj r f v out 16-bit latch serial input register 16-bit dac i out control logic ref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ad1860 ? s dgnd nc clk le data ? l +v l nc no connect = +v s trim msb adj i out agnd sj r f v out 18-bit latch serial input register 18-bit dac i out control logic ref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ad1862 ? s ? s +v l clk le data ? l trim +v s nr 2 adj nr 1 agnd i out r f dgnd voltage reference input & digital offset 20-bit dac ad1856 16-bit audio dac complete, no external components required 0.0025% thd low cost 16-pin dip or soic package standard pinout ad1860 18-bit audio dac complete, no external components required 0.0025% thd+n 108 db signal-to-noise ratio 16-pin dip or soic package standard pinout ad1862 20-bit audio dac 119 db signal-to-noise ratio 0.0016% thd+n 102 db d-range performance 1 db gain linearity 16-pin dip package ad1868 +5 v single supply dual 18-bit audio dac no external components required 0.004% thd+n 92 db d-range performance 3 db gain linearity 16-pin dip or soic package 18-bit dac 18-bit serial register ad1868 v l ll dl clk dr lr dgnd v bias r v bias l v s v out l nrl agnd nrr v out r v s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18-bit dac 18-bit serial register v ref v ref obsolete
ad1865 rev. 0 C12C outline dimensions dimensions shown in inches and (mm). 24-pin plastic dip (n-24a) package 0.100 (2.54) bsc 11 2 13 24 0.070 (1.77) 0.030 (0.77) 0.580 (14.73) 0.485 (12.32) 0.625 (15.87) 0.600 (15.24) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 1.290 (32.70) 1.150 (29.30) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) pin 1 0.250 (6.35) 0.200 (5.05) 0.125 (3.18) seating plane 28-pin soic (r-28) package 0.050 (1.27) bsc 0.019 (0.49) 0.014 (0.35) 0.096 (2.44) 0.089 (2.26) 0.01 (0.254) 0.006 (0.15) 1 14 15 28 0.708 (18.02) 0.696 (17.67) 0.299 (7.6) 0.291 (7.39) 0.414 (10.52) 0.398 (10.10) 0.042 (0.32) 0.009 (0.23) 0.013 (0.32) 0.009 (0.23) 0.003 (0.76) 0.02 (0.51) 6 0 c1468C8C8/91 printed in u.s.a. obsolete

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